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IIT Delhi Micro-GPU Runs on Spartan-7 FPGA, With 65nm ASIC Roadmap

By AiCybr Editorial · Published September 24, 2026

IIT Delhi researchers announced on September 24, 2026 that they have demonstrated a programmable micro-GPU implemented entirely in Register Transfer Language (RTL) and mapped to a Spartan-7 FPGA. The custom floating-point graphics engine renders programmable graphics and is intended as reusable processor IP for embedded display and visualization systems.

The institute describes the prototype as, to the researchers' knowledge, the first working and demonstrable indigenously designed micro-GPU from a university in India. The current implementation is an FPGA research prototype. The team's roadmap calls for an 8–16-core vector-style graphics architecture, an optimized compiler and graphics software toolchain, followed by a proof-of-concept implementation on a 65nm ASIC process.

That distinction matters for evaluating the work technically. The demonstrated artifact establishes a programmable GPU architecture on reconfigurable hardware; the planned multi-core design and fabricated silicon remain future development stages. IIT Delhi has not published throughput, clock frequency, power, memory-bandwidth, die-area or standardized GPU benchmark results for the prototype in its announcement.

What IIT Delhi demonstrated

The project was led by M.Tech students Nammi Akash and M. Ravi Teja under Prof. Jayadeva and Prof. Kaushik Saha in IIT Delhi's Electrical Engineering Department.

According to IIT Delhi, the team built a custom floating-point GPU engine in RTL and mapped the design to a Spartan-7 FPGA platform. RTL describes the digital hardware at the register-transfer level, allowing the architecture to be synthesized into programmable logic now and potentially implemented as an ASIC later.

The demonstrated system therefore sits at an earlier hardware-development stage than a fabricated commercial GPU. Its immediate technical value is the processor architecture and the ability to execute programmable graphics on standard FPGA hardware.

Item Current status
Processor Custom programmable micro-GPU
Arithmetic Floating-point GPU engine
Hardware description RTL
Demonstration platform Spartan-7 FPGA
Demonstrated workload Programmable graphics rendering
Intended use Embedded graphics and display processing
Future architecture 8–16-core vector-style GPU
Future software Optimized compiler and graphics toolchain
Planned silicon step 65nm ASIC proof of concept

Why Spartan-7 is useful at this stage

An FPGA allows a research team to synthesize, test and revise a processor architecture without first paying for a custom silicon tape-out. The same RTL-oriented development approach can also expose timing, resource-use and architectural problems before an ASIC implementation is attempted.

IIT Delhi says the architecture is scalable processor IP that can be mapped either to an FPGA or to an ASIC. The current Spartan-7 implementation is therefore a validation platform for the architecture, while the proposed 65nm ASIC would test how the design translates into fixed silicon.

The announcement does not identify the exact Spartan-7 device, FPGA resource utilization, operating frequency or external-memory configuration. Those figures would be needed for a detailed comparison with other embedded graphics processors, so no performance ranking can be established from the available evidence.

The 8–16-core and 65nm roadmap

The next planned phase expands the project into an 8–16-core vector-style graphics processor. The team also intends to develop an optimized compiler and graphics software toolchain around it.

That software work is consequential. A programmable processor needs a practical path from applications and graphics operations to instructions the hardware can execute. A compiler and graphics stack can determine whether research IP becomes usable beyond hand-built demonstrations.

The researchers then plan to move toward a proof of concept on a 65nm ASIC process node. A mature process can be appropriate for cost-sensitive embedded hardware where leading-edge transistor density is less important than development cost, availability and integration with the target system.

IIT Delhi has presented 65nm as a roadmap target, not a fabricated chip currently available for evaluation. The team says it plans to seek funding for ASIC development, system integration and eventual commercialization.

Target applications are embedded displays

The institute's stated application set is substantially narrower than the workloads associated with datacenter AI accelerators or high-end PC GPUs. Proposed uses include:

  • industrial control displays;
  • low-cost human-machine interfaces;
  • e-rickshaw dashboard navigation;
  • inland-water navigation terminals for small fishing boats;
  • educational e-book readers; and
  • other affordable embedded visualization systems.

These workloads help explain the project's emphasis on a compact programmable architecture and a mature-node ASIC roadmap. They can benefit from locally controlled graphics IP without requiring the scale of a modern discrete gaming or AI accelerator.

The institute notes that GPUs are also important to AI and machine learning systems, but its September 24 announcement provides no AI/ML benchmark or dedicated tensor/matrix-acceleration specification for this prototype. The demonstrated capability is programmable graphics rendering.

How to interpret the "indigenous micro-GPU" claim

IIT Delhi's precise formulation is useful: the researchers say that, to the best of their knowledge, this is the first working, demonstrable indigenously designed micro-GPU from a university in India. That is the scope used here.

The claim concerns the team's processor design and working FPGA implementation. The Spartan-7 itself is the programmable device hosting the RTL design, while the proposed 65nm ASIC is a later roadmap step.

Independent reports from Press Trust of India and Business Standard corroborate the September 24 announcement, the Spartan-7 implementation and the 8–16-core/65nm roadmap. They do not provide additional benchmark data that would support a broader performance claim.

What would make the next milestone technically significant

The most informative next release would expose implementation data for the expanded architecture: core count, clock frequency, FPGA or ASIC area, memory interface and bandwidth, supported graphics operations, compiler maturity, power consumption and repeatable rendering benchmarks.

A fabricated 65nm proof of concept would add a second important validation layer by showing how the architecture behaves as fixed silicon. A usable compiler and graphics toolchain would then determine how accessible the processor is to application developers.

For now, the September 24 result is best evaluated as an indigenous programmable graphics-processor architecture demonstrated on FPGA hardware, with a defined path toward a larger vector design and mature-node ASIC prototype.

Bottom line

IIT Delhi has demonstrated a custom floating-point micro-GPU in RTL on a Spartan-7 FPGA and outlined a concrete next-stage architecture: 8–16 vector-style cores, an optimized software toolchain and a 65nm ASIC proof of concept. The current evidence establishes programmable graphics rendering on FPGA hardware. Performance, power and silicon characteristics await later implementation and measurement.

Sources

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