CXMT Says Fifth-Generation DRAM Platform Is in Mass Production, Shows 24Gb LPDDR5X

By AiCybr Editorial · Published September 20, 2026

Chinese DRAM manufacturer ChangXin Memory Technologies (CXMT) says its fifth-generation memory technology platform has entered mass production, with denser cell geometry and higher wafer productivity than its previous process. The company disclosed the platform at the World Manufacturing Convention in Hefei on September 20, 2026, according to Reuters.

CXMT says the process uses quadruple patterning and reduces memory-cell feature spacing to 11.95 nanometres. The company reports that gross die output per wafer increases by at least 50% compared with its previous generation, alongside lower cost and power consumption. Those are CXMT's process claims; public independent yield and cost data for the new platform are not yet available.

At the same event, CXMT introduced two 24-gigabit LPDDR5X dies, a 50% density increase over the 16Gb die capacity in the company's previously published LPDDR5X portfolio. The announcement expands the density options available to device makers, while CXMT's current public product page still describes its established LPDDR5X die portfolio as 12Gb and 16Gb. The event disclosure therefore establishes the new 24Gb products, while broader customer availability and device qualification remain separate milestones.

What CXMT announced

The process announcement matters because DRAM economics depend heavily on the number of usable bits a manufacturer can obtain from each wafer. Higher density can increase the amount of memory produced from the same wafer area, provided manufacturing yield remains competitive. CXMT has not published the yield data needed to calculate a comparable cost per usable gigabit for the new platform.

Why quadruple patterning matters

Advanced memory manufacturing requires increasingly fine structures. CXMT has developed the new platform around multiple-patterning techniques, an approach that can form smaller features with deep-ultraviolet lithography by splitting a dense pattern across several exposures and processing steps.

That approach can extend existing lithography equipment to finer geometries, though additional patterning steps increase process complexity. CXMT's reported 11.95nm feature spacing is therefore a useful manufacturing indicator, while it should not be read as a directly comparable logic-foundry node label such as “12nm.” DRAM makers use different structures, process definitions and density metrics from logic foundries.

Reuters reports that CXMT developed the process through extensive simulation and collaboration with Chinese semiconductor-equipment suppliers. The manufacturing disclosure is significant for China's domestic memory supply because advanced lithography equipment remains subject to export controls.

The 24Gb LPDDR5X density step

A 24Gb memory die contains 3GB of raw capacity. Compared with a 16Gb die, the new density provides 50% more capacity per die before packaging and system-level configuration are considered.

Higher-density dies can give device designers more flexibility in reaching large memory capacities with fewer dies or packages. The practical benefit depends on package design, memory channels, validated data rates, power characteristics and the host SoC's memory controller.

CXMT's public LPDDR5X product information before this announcement listed 12Gb and 16Gb dies with speeds up to 10,667Mbps. Its earlier LPDDR5X portfolio entered mass production at 8,533Mbps and 9,600Mbps in May 2025, while the 10,667Mbps version was initially disclosed as customer sampling in October 2025. CXMT subsequently moved its faster mobile-memory products forward, including LPDDR6.

CXMT already has LPDDR6 in production

The fifth-generation platform announcement follows a separate mobile-memory milestone. On September 7, CXMT announced mass production of a 16GB LPDDR6 package built from 16Gb dies, with a maximum specified rate of 12,800Mbps and a 1,295-ball FBGA package compliant with the JEDEC LPDDR6 standard.

CXMT says that LPDDR6 package delivers up to 60% higher peak bandwidth than 10,667Mbps LPDDR5X and consumes 20% less power in its internal comparison. The first disclosed commercial deployment is Xiaomi's 18 Fold. CXMT's specification says the memory operates at 10,667Mbps when paired with that device's SoC.

The September 20 process announcement and the earlier LPDDR6 product launch describe different layers of CXMT's roadmap: one concerns the manufacturing platform and new 24Gb LPDDR5X density, while the other is a shipping memory standard and package implementation.

What to watch next

For PC, mobile and server buyers, the most useful follow-up evidence will be customer qualification, package configurations, sustained production volume and independent device availability. For semiconductor analysis, yield and cost per bit will determine how much of the reported wafer-density improvement converts into commercial advantage.

CXMT already lists DDR5 dies at 16Gb and 24Gb and LPDDR6 as a production product. The new 24Gb LPDDR5X disclosure extends that higher-density strategy into the mature LPDDR5X ecosystem, where a large installed base of mobile SoCs and devices can continue to use the standard.

Bottom line

CXMT's fifth-generation DRAM platform is a manufacturing-scale announcement: the company says it is in mass production, uses quadruple patterning to reach 11.95nm feature spacing, and raises gross die output per wafer by at least 50% over its previous generation. The accompanying 24Gb LPDDR5X dies increase die density by 50% over CXMT's previously published 16Gb maximum for that family.

The next decision-relevant milestones are customer qualification and independently observable production economics. Those will show how the new process translates from CXMT's manufacturing claims into device supply, cost per bit and competitive market volume.

Sources: Reuters, “China's CXMT says new memory-chip platform enters mass production” (September 20, 2026); CXMT product documentation; CXMT, “CXMT Pioneers Mass-Production of LPDDR6” (September 7, 2026); CXMT, “CXMT Announces LPDDR5X Mass Production” (October 28, 2025).