Huawei Ascend 960 Roadmap: 960DT, 960PR and the Atlas 960 SuperPoD
Huawei has expanded its 2027 AI-accelerator roadmap with two Ascend 960 variants: the 960DT planned for the first quarter of 2027 and the 960PR planned for the third quarter. The schedule adds product-level detail to Huawei's previously published Ascend 960 architecture and its Atlas 960 SuperPoD, which remains scheduled for the fourth quarter of 2027.
Huawei's existing technical roadmap assigns the Ascend 960 up to 2 PFLOPS of FP8 compute and 4 PFLOPS of FP4 compute per chip, twice the corresponding compute figures published for the Ascend 950 series. The company also says the 960 generation will double memory capacity, memory-access bandwidth and interconnect-port count relative to Ascend 950.
At system scale, Huawei's published Atlas 960 SuperPoD design combines as many as 15,488 Ascend 960 chips and targets 30 EFLOPS FP8, 60 EFLOPS FP4, 4,460 TB of memory and 34 PB/s of interconnect bandwidth. A planned Atlas 960 SuperCluster extends that architecture beyond one million NPUs.
Huawei's current Ascend 960 roadmap
| Product | Planned availability | Published role or scale |
|---|---|---|
| Ascend 960DT | Q1 2027 | Newly identified Ascend 960 variant |
| Ascend 960PR | Q3 2027 | Newly identified Ascend 960 variant |
| Atlas 960 SuperPoD | Q4 2027 | Up to 15,488 Ascend 960 chips |
| Atlas 960 SuperCluster | Q4 2027 | More than 1 million NPUs |
Huawei disclosed the 960DT and 960PR timing on September 17, 2026, according to Reuters reporting from the company's event in Shanghai. The company had already published the broader Ascend 960 and Atlas 960 roadmap in September 2025. The newer disclosure therefore refines the 960 family schedule instead of marking the first announcement of the architecture.
The 960DT and 960PR suffixes are now part of Huawei's public roadmap reporting. Detailed per-variant specifications have yet to be published in the technical material reviewed for this article, so the architecture-level figures below apply to Huawei's published Ascend 960 roadmap rather than being assigned separately to either new variant.
Ascend 960 architecture: published specifications
Huawei's technical roadmap positions Ascend 960 as the third generation in a sequence that begins with Ascend 950PR and 950DT. The company published the following architecture-level targets for Ascend 960:
| Specification | Ascend 960 published target |
|---|---|
| FP8 compute | 2 PFLOPS |
| FP4 compute | 4 PFLOPS |
| Memory capacity | 2× Ascend 950 generation |
| Memory-access bandwidth | 2× Ascend 950 generation |
| Interconnect ports | 2× Ascend 950 generation |
| Additional numeric format | Huawei HiF4 |
| Architecture direction | Combined SIMD and SIMT design |
For context, Huawei lists Ascend 950 at 1 PFLOPS FP8 and 2 PFLOPS FP4. The company says the 960 generation also adds HiF4, its proprietary 4-bit data format, while retaining support across a broader set of training and inference formats.
These are Huawei roadmap specifications for future silicon. They describe the company's design targets and should be evaluated as such until production hardware and independently measured systems are available.
Atlas 960 scales the chip into a 15,488-NPU SuperPoD
Huawei's system strategy centers on SuperPoDs: multiple physical machines connected so that software can use the installation as a large logical compute system. The Atlas 960 SuperPoD is the planned 2027 implementation around Ascend 960.
Huawei's published full configuration contains 15,488 Ascend 960 chips across 220 cabinets: 176 compute cabinets and 44 communications cabinets. The company specifies a deployment footprint of about 2,200 square metres.
| Atlas 960 SuperPoD target | Published figure |
|---|---|
| Ascend 960 chips | Up to 15,488 |
| Cabinets | 220 |
| Compute cabinets | 176 |
| Communications cabinets | 44 |
| FP8 compute | 30 EFLOPS |
| FP4 compute | 60 EFLOPS |
| Memory | 4,460 TB |
| Interconnect bandwidth | 34 PB/s |
| Planned availability | Q4 2027 |
Huawei also publishes workload-level targets of 15.9 million tokens/s for training and 80.5 million tokens/s for inference for the Atlas 960 SuperPoD. These are vendor projections for a future system, not independent production benchmarks.
UnifiedBus is the scale-out layer
The 960 roadmap is tied to Huawei's UnifiedBus interconnect architecture. Huawei designed UnifiedBus to connect thousands of NPUs inside a SuperPoD and to extend the same approach into larger SuperClusters.
Huawei describes six design properties for the SuperPoD architecture: bus-grade interconnect, peer-to-peer coordination, resource pooling, a unified protocol, large-scale networking and high availability. Its UBoE mode carries UnifiedBus over Ethernet so deployments can use Ethernet switching infrastructure at cluster scale.
The company says it has developed 11 semiconductors around UnifiedBus for its large systems. On September 17, Reuters reported that Huawei had shipped more than 1,000 Supernodes to more than 370 customers, while the company's largest planned SuperClusters can scale to roughly one million processors. The shipment figure describes Huawei's broader connected-system portfolio, not Atlas 960 shipments.
How the 2027 schedule fits the older roadmap
Huawei's September 2025 roadmap placed the Ascend 960 generation after the 950 series and scheduled the Atlas 960 SuperPoD for Q4 2027. The September 2026 disclosure adds two earlier chip milestones inside that same year: 960DT in Q1 and 960PR in Q3.
That sequence gives Huawei time between individual chip availability and the planned full-scale Atlas 960 system. It also mirrors the company's use of separate 950-series variants for different workload phases, although Huawei has not yet published enough 960DT/960PR technical detail to map each new suffix to a specific training or inference role with confidence.
For infrastructure planners, the important confirmed timeline is therefore a staged 2027 rollout: first 960DT, then 960PR, followed by the Atlas 960 SuperPoD and SuperCluster targets in Q4.
What to watch before deployment decisions
The roadmap is unusually specific at the architecture and system level, but deployment decisions will depend on production details that arrive closer to launch. The highest-value data will be per-variant memory capacity and bandwidth, board and server form factors, power requirements, software-stack compatibility, production availability, pricing and measured training/inference performance.
Huawei's scale-out strategy also makes interconnect efficiency central. A 15,488-chip SuperPoD depends on collective communication, scheduling, reliability and software efficiency in addition to nominal accelerator throughput. Production benchmarks will determine how much of the published aggregate compute can be sustained on real model workloads.
Bottom line
Huawei's September 2026 update turns Ascend 960 from a single future architecture milestone into a more concrete 2027 product sequence. The 960DT is planned for Q1, the 960PR for Q3, and the Atlas 960 SuperPoD and SuperCluster for Q4 2027.
The existing architecture targets remain substantial: 2 PFLOPS FP8 and 4 PFLOPS FP4 per Ascend 960 chip, with a 15,488-chip Atlas 960 design targeting 30 EFLOPS FP8, 60 EFLOPS FP4 and 34 PB/s of interconnect bandwidth. Those figures are roadmap targets until production systems provide measured results.
Sources
- Huawei, “Groundbreaking SuperPoD Interconnect: Leading a New Paradigm for AI Infrastructure,” published September 2025: https://www.huawei.com/en/news/2025/9/hc-xu-keynote-speech
- Huawei, “Huawei Unveils World's Most Powerful SuperPoDs and SuperClusters,” September 18, 2025: https://www.huawei.com/en/news/2025/9/hc-lingqu-ai-superpod
- Reuters, “China's Huawei sets 2027 launch for new AI chips as it targets Nvidia,” September 17, 2026: https://www.reuters.com/world/asia-pacific/chinas-huawei-launch-two-new-ai-chips-2027-2026-09-17/