GPT-Synopsys Brings OpenAI Models Into Chip Design and Verification Workflows
Synopsys and OpenAI announced GPT-Synopsys on September 30, 2026, a specialized AI model being developed to operate Synopsys electronic design automation tools across semiconductor design and verification workflows. The companies signed a multi-year agreement covering joint development, go-to-market work and revenue sharing.
GPT-Synopsys is designed to accept engineering objectives such as power, performance and area (PPA) optimization, timing closure and verification closure, run the relevant Synopsys tools, interpret their outputs, modify the design and iterate toward a verified result for engineer review. Early technology engagements are already underway with semiconductor customers, according to Synopsys.
The model will run on OpenAI-hosted infrastructure and integrate with Synopsys.ai and Synopsys Autopilot. Synopsys also says it will interoperate with customer agent harness systems, placing the service as an AI execution layer around established EDA flows.
How GPT-Synopsys fits into the EDA workflow
Traditional semiconductor design relies on repeated optimization and sign-off cycles across synthesis, physical implementation, timing, power and verification tools. Synopsys says GPT-Synopsys will learn to use those tools as an expert operator: selecting actions, interpreting engineering outputs and iterating on a design objective.
| Area | Announced GPT-Synopsys role |
|---|---|
| PPA | Explore and optimize power, performance and area trade-offs |
| Timing | Run tools and iterate toward timing closure |
| Verification | Operate verification workflows and work toward closure |
| Tool operation | Directly use Synopsys EDA tools and interpret outputs |
| Human control | Produce outcomes for engineer review |
| Integration | Synopsys.ai, Synopsys Autopilot and customer agent harnesses |
| Infrastructure | OpenAI-hosted |
OpenAI will license Synopsys EDA tools for development of the specialized model. That arrangement gives the model access to the same engineering software used to evaluate whether proposed design changes satisfy physical and verification constraints.
Verification remains part of the design loop
The announced workflow keeps established EDA tools in the loop. GPT-Synopsys can propose and execute design changes, while tool outputs provide the engineering measurements used to judge PPA, timing and verification results. Reuters reports that Synopsys expects conventional computing-based sign-off verification to continue validating model output for physical correctness.
That distinction matters for semiconductor engineering because an apparently plausible RTL or layout change still has to satisfy deterministic design rules, timing constraints and other sign-off requirements before manufacturing.
Deployment and data controls
Synopsys says the joint service will bundle compute, model access and licenses. General customer pricing and a broad availability date remain unannounced.
The announced enterprise controls include encryption for customer data at rest and in transit, configurable retention, audit and permission controls, and exclusion of customer-specific design data from model training.
The service is intended to interoperate with customer agent harnesses. That could let semiconductor teams place GPT-Synopsys inside existing orchestration and review systems while retaining Synopsys tools as the execution and validation layer.
Why this is significant for chip design
AI is already being added to EDA products for optimization and workflow automation. GPT-Synopsys extends that approach by training a specialized model to operate the tools themselves across longer engineering loops.
If the system performs as described in production, the practical gain would come from increasing the number of design alternatives engineers can evaluate and automating repetitive tool-run, interpretation and adjustment cycles. Production evidence for design quality, closure time, compute use and engineering effort will determine the measurable value after customer deployment.
The partnership also creates a direct commercial link between a frontier-model provider and one of the major EDA vendors. Synopsys announced the project alongside a broader strategy to expand AI-driven engineering and agentic workflows across its design and simulation portfolio.
Bottom line
GPT-Synopsys is a specialized chip-design model built around direct operation of Synopsys EDA tools, with PPA optimization, timing and verification closure among its stated workflows. The architecture keeps established engineering tools and human review in the loop while adding an agentic model capable of running and interpreting iterative design tasks. Early customer engagements are underway; pricing and broad availability remain to be announced.
Sources
- Synopsys and OpenAI announcement, September 30, 2026: https://news.synopsys.com/2026-09-30-OpenAI-and-Synopsys-Announce-GPT-Synopsys-Frontier-Intelligence-to-Revolutionize-Chip-Design
- Synopsys 2026 Investor Day strategy announcement: https://news.synopsys.com/2026-09-30-Synopsys-Details-Growth-Strategy-and-Long-term-Financial-Model-at-2026-Investor-Day
- Reuters, September 30, 2026: https://www.reuters.com/business/synopsys-openai-strike-deal-develop-ai-model-chip-design-work-2026-09-30/