Dnotitia VDPU: Vector-Search ASIC Enters Silicon Testing for AI Retrieval
Dnotitia has received the first fabricated samples of its Vector Data Processing Unit (VDPU), a dedicated accelerator for vector-search workloads used in retrieval-augmented generation and agentic AI systems. Chip-level characterization is underway, with ASIC-based evaluations planned for Q4 2026.
The company also disclosed server-scale results from its earlier FPGA implementation. A server fitted with four VDPU cards delivered up to 5.77x the vector-search throughput of a dual-socket CPU-only server running the same software stack, according to Dnotitia. In a 4,096-dimensional multimodal index-building workload, the FPGA system reduced host CPU use by 92% and host memory use by 73%.
The 5.77x, 92% and 73% figures are vendor-reported FPGA measurements. Dnotitia is targeting up to 10x vector-search performance versus a CPU-based server for the eventual ASIC system; silicon characterization and Q4 evaluations will establish the ASIC's production performance.
What the VDPU accelerates
Vector search is the retrieval stage behind many RAG systems. Documents, images or other data are represented as numerical embeddings, and the system searches a vector index for items close to a query embedding before relevant context is supplied to a language or multimodal model.
As agent workflows perform repeated searches, retrieval can consume substantial CPU cycles and memory bandwidth alongside model inference. Dnotitia's architecture moves that vector-processing work onto dedicated hardware so host CPUs remain available for application logic while GPU or accelerator memory remains focused on model execution.
The FPGA platform has been validated with FAISS, Milvus and hnswlib, according to the company. Supported index approaches in those evaluations include brute-force KNN, IVF, NSW and HNSW. Dnotitia says it plans broader vector-library and database support on the ASIC.
Current development status
| Item | Status / result |
|---|---|
| First-generation VDPU ASIC | First samples returned from fabrication |
| Current phase | Chip-level characterization |
| ASIC system evaluations | Planned for Q4 2026 |
| FPGA server configuration | Four VDPU cards |
| Reported FPGA vector-search throughput | Up to 5.77x dual-socket CPU-only server |
| 4,096-D index-build host CPU reduction | 92% |
| 4,096-D index-build host memory reduction | 73% |
| ASIC performance target | Up to 10x CPU-based server |
| Validated FPGA software | FAISS, Milvus, hnswlib |
For capacity planning, the current benchmark evidence describes the FPGA evaluation platform under Dnotitia's test conditions. Q4 silicon evaluation should add production-relevant measurements including power consumption, throughput, latency across broader datasets and system economics.
Why dedicated retrieval silicon could matter
Modern AI infrastructure commonly separates storage, retrieval and model inference logically while executing retrieval largely on CPUs or GPUs. Dedicated vector hardware creates another option: keep high-dimensional similarity-search operations on a specialized accelerator and reserve general-purpose compute for orchestration and inference.
That architecture becomes more relevant as agentic systems increase retrieval frequency. A conventional RAG request may retrieve context once or a few times. A long-running agent can search, verify, revise a query and retrieve again across many steps. Retrieval throughput and index-building overhead can therefore become infrastructure constraints even when sufficient model-inference capacity is available.
Dnotitia's reported host-resource reductions are particularly relevant here. If similar behavior carries into production silicon, operators could potentially increase retrieval throughput without scaling CPU and memory capacity at the same rate. Actual system economics will depend on final card cost, power, software integration and workload-specific performance.
Compatibility is central to adoption
Specialized accelerators face a software problem as much as a silicon problem. Existing AI retrieval stacks are already built around established vector libraries and databases, so replacing the application layer to use new hardware would raise deployment friction.
Dnotitia is addressing that issue by integrating VDPU with its Seahorse vector database while validating common software including FAISS, Milvus and hnswlib. Support for multiple index types also matters because vector workloads vary substantially by recall target, vector dimensionality, dataset size, update frequency and latency requirement.
For infrastructure teams, the practical evaluation should use the same database, index configuration, embedding dimensions, recall target and concurrency expected in production. A throughput multiple measured with a different recall or index strategy can produce a misleading capacity comparison.
What Q4 silicon tests need to establish
The first ASIC evaluations should provide a clearer view of four deployment questions.
Performance at target recall: throughput and latency need to be compared at equivalent recall levels across realistic vector dimensions and dataset sizes.
Host offload: CPU and memory savings should be measured during both index construction and sustained query workloads, including concurrent application activity.
Power and density: dedicated retrieval silicon becomes more compelling when higher search throughput also improves performance per watt and per server slot.
Software coverage: production value depends on stable integration with the vector databases, libraries, monitoring and orchestration systems already used in AI infrastructure.
Dnotitia has begun discussions with server, storage, memory, semiconductor and vector-database partners as it prepares the Q4 evaluation phase. Commercial pricing and general availability remain future commercialization milestones; Q4 evaluation is the next announced step.
Bottom line
Dnotitia's VDPU has moved from FPGA evaluation to fabricated ASIC samples, with silicon characterization underway and system evaluations planned for Q4 2026. The company's FPGA platform reports up to 5.77x the vector-search throughput of a dual-socket CPU server, plus substantial host CPU and memory reductions during a 4,096-dimensional index-building workload.
The next milestone is silicon evidence. Strong retrieval throughput, host offload and software compatibility at competitive power and cost would make dedicated vector processing a potentially useful infrastructure tier for retrieval-heavy RAG and agent deployments.